Method of producing semiconductor

ABSTRACT

In a conventional SGT production method, during dry etching for forming a pillar-shaped silicon layer and a gate electrode, an etching amount cannot be controlled using an end-point detection process, which causes difficulty in producing an SGT while stabilizing a height dimension of the pillar-shaped silicon layer, and a gate length. In an SGT production method of the present invention, a hard mask for use in dry etching for forming a pillar-shaped silicon layer is formed in a layered structure comprising a first hard mask and a second hard mask, to allow the end-point detection process to be used during the dry etching for the pillar-shaped silicon layer. In addition, a gate conductive film for use in dry etching for forming a gate electrode is formed in a layered structure comprising a first gate conductive film and a second gate conductive film, to allow the end-point detection process to be used during the dry etching for the gate electrode.

RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.12/703,980 filed on Feb. 11, 2010, which, pursuant to 35 U.S.C. §119(e),claims the benefit of the filing date of Provisional U.S. PatentApplication Ser. No. 61/207,554 filed on Feb. 13, 2009 and also is acontinuation application of PCT/JP2009/052144 filed on Feb. 9, 2009which claims priority under 35 U.S.C. §365(a) to PCT/JP2008/052150 filedon Feb. 8, 2008. The entire contents of these applications are herebyincorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a production method for a semiconductordevice, and more particularly to a production method for an SGT(Surrounding Gate Transistor) which is a vertical MOS transistorcomprising a pillar-shaped semiconductor layer having a sidewall servingas a channel region, and a gate electrode formed to surround the channelregion.

2. Description of the Related Art

With a view to achieving higher integration and higher performance of asemiconductor device, an SGT (Surrounding Gate Transistor) has beenproposed which is a vertical transistor comprising a pillar-shapedsemiconductor layer formed on a surface of a semiconductor substrate,and a gate formed to surround a sidewall of the pillar-shapedsemiconductor layer (see, for example, the following Patent Document 1:JP 2-188966A). In the SGT, a drain, a gate and a source are arranged ina vertical direction, so that an occupancy area can be significantlyreduced as compared with a conventional planar transistor.

FIG. 20( a) shows a top plan view of a CMOS inverter constructed usingthe SGT disclosed in the Patent Document 1, and FIG. 20( b) is asectional view taken along the cutting-plane line A-A′ in the top planview of FIG. 20( a).

Referring to FIGS. 20( a) and 20(b), an N-well 302 and a P-well 303 areformed in an upper region of a Si substrate 301. A pillar-shaped siliconlayer 305 constituting a PMOS (PMOS pillar-shaped silicon layer 305) anda pillar-shaped silicon layer 306 constituting an NMOS (NMOSpillar-shaped silicon layer 306) are formed on a surface of the Sisubstrate, specifically, on respective ones of the N-well region and theP-well region, and a gate 308 is formed to surround the pillar-shapedsilicon layers. Each of a P⁺ drain diffusion layer 310 formed underneaththe PMOS pillar-shaped silicon layer, and a N⁺ drain diffusion layer 312formed underneath the NMOS pillar-shaped silicon layer, is connected toan output terminal Vout. A source diffusion layer 309 formed on a top ofthe PMOS pillar-shaped silicon layer is connected to a power supplypotential Vcc, and a source diffusion layer 311 formed on a top of theNMOS pillar-shaped silicon layer is connected to a ground potential Vss.The common gate 308 for the PMOS and the NMOS is connected to an inputterminal Vin. In this manner, the CMOS inverter is formed.

A process flow as one example of an SGT production method is disclosedin the following Non-Patent Document 1. FIGS. 21( a) to 21(h)schematically show the process flow for forming a pillar-shaped siliconlayer and a gate electrode of an SGT, in the Non-Patent Document 1. Withreference to FIGS. 21( a) to 21(h), the process flow will be describedbelow. As shown in FIG. 21( b), a silicon substrate 402 illustrated inFIG. 21( a) is prepared, and etched to form a pillar-shaped siliconlayer 403. Then, as shown in FIG. 21( c), a gate dielectric film 404 isformed. Then, as shown in FIG. 21( d), a gate conductive film 405 isformed. Then, as shown in FIG. 21( e), the gate conductive film 405, anda portion of the gate dielectric film 404 on a top of the pillar-shapedsilicon layer, are polished by chemical mechanical polishing (CMP).Then, as shown in FIG. 21( f), the gate conductive film 405 is etchedback to allow the gate conductive film 405 surrounding the pillar-shapedsilicon layer to have a desired gate length. Then, as shown in FIG. 21(g), a resist 406 for a gate line pattern is formed by lithography. Then,as shown in FIG. 21( h), the gate conductive film 405 is etched to forma gate electrode and a gate line.

However, the SGT production method illustrated in FIGS. 21( a) to 21(h)has the following problems.

Firstly, in the above process flow, dry etching for the pillar-shapedsilicon layer has to be performed under etching conditions including adesignated etching time, because it is unable to employ an end-pointdetection process based on monitoring of a change in plasma emissionintensity. In this case, a height dimension of the pillar-shaped siliconlayer is directly influenced by an etching rate of an etching apparatusduring an etching operation, so that it will considerably fluctuate. Inan SGT, a fluctuation in height dimension of a pillar-shaped siliconlayer has a direct impact on a fluctuation in channel length, whichcauses a considerable fluctuation in transistor characteristics.

Secondly, in the above process flow, dry etching for a gate electrodealso has to be performed under etching conditions including a designatedetching time, because it is unable to employ the end-point detectionprocess based on monitoring of a change in plasma emission intensity. Inthis case, a gate length is directly influenced by an etching rate of anetching apparatus during an etching operation, so that it willconsiderably fluctuate. The fluctuation in gate length inevitably causesa considerable fluctuation in transistor characteristics.

Thus, in the above SGT production method, due to considerable influenceof the etching rate during the etching operation on the height dimensionand the gate length of the pillar-shaped silicon layer, it is extremelydifficult to minimize a fluctuation in transistor characteristicsbetween wafers or production lots.

In view of the above circumstances, it is an object of the presentinvention to produce a semiconductor device while stabilizing a heightdimension of a pillar-shaped semiconductor layer, and a gate length, byusing an end-point detection process based on monitoring of a plasmaemission intensity, during dry etching for forming the pillar-shapedsemiconductor layer and during dry etching for setting the gate length.

-   Patent Document 1: JP 2-188966A-   Non-Patent Document 1: Ruigang Li, et al., “50 nm Vertical    Surrounding Gate MOSFET with S-Factor of 75 mV/dec”, Device Research    Conference, 2001, p. 63

SUMMARY OF THE INVENTION

In order to produce a semiconductor device while stabilizing a heightdimension of a pillar-shaped semiconductor layer, according to a firstaspect of the present invention, there is provided a method of producinga semiconductor device in which a source diffusion layer, a draindiffusion layer and a pillar-shaped semiconductor layer are verticallyarranged on an upper side of a substrate in a layered manner, and a gateis arranged around a sidewall of the pillar-shaped semiconductor layer.The method comprises: providing a first protective film arranged on asemiconductor substrate, and a second protective film arranged on thefirst protective film, wherein the second protective film has a plasmaemission characteristic different from that of the first protectivefilm, and the first and second protective films are patterned in apillar shape on the semiconductor substrate; and etching thesemiconductor substrate using the first and second protective films as amask to allow a part of the semiconductor substrate to be formed as apillar-shaped silicon layer, wherein an intensity of plasma emissiongenerated from the second protective film is monitored during theetching to detect a change in the plasma emission intensity occurringwhen the second protective film is etched away, to thereby detect anend-point of the etching for the pillar-shaped silicon layer.

Preferably, in the method of the present invention, the secondprotective film is made of polysilicon or amorphous silicon.

In order to produce a semiconductor device while stabilizing a gatelength, according to a second aspect of the present invention, there isprovided a method of producing a semiconductor device in which a sourcediffusion layer, a drain diffusion layer and a pillar-shapedsemiconductor layer are vertically arranged on an upper side of asubstrate in a layered manner, and a gate is arranged around a sidewallof the pillar-shaped semiconductor layer, wherein the pillar-shapedsemiconductor layer is arranged on a semiconductor substrate, and adielectric film is arranged on respective surfaces of the semiconductorsubstrate and the pillar-shaped semiconductor layer. The methodcomprises the steps of: forming a first gate conductive film to cover asurface of the dielectric film; forming, on a surface of the first gateconductive film, a second gate conductive film having a plasma emissioncharacteristic different from that of the first gate conductive film;flattening respective upper portions of the first and second gateconductive films; and anisotropically etching the first and second gateconductive films, wherein an intensity of plasma emission generated fromthe second gate conductive film is monitored during the etching todetect a change in the plasma emission intensity occurring when thesecond gate conductive film is etched away, to thereby detect anend-point of the etching for the first and second gate conductive films.

In order to produce a semiconductor device while stabilizing a gatelength, according to a third aspect of the present invention, there isprovided a method of producing a semiconductor device in which a sourcediffusion layer, a drain diffusion layer and a pillar-shapedsemiconductor layer are vertically arranged on an upper side of asubstrate in a layered manner, and a gate is arranged around a sidewallof the pillar-shaped semiconductor layer, wherein the pillar-shapedsemiconductor layer is arranged on a semiconductor substrate, and adielectric film is arranged on respective surfaces of the semiconductorsubstrate and the pillar-shaped semiconductor layer. The methodcomprises the steps of: forming a first gate conductive film to cover asurface of the dielectric film; forming, on a surface of the first gateconductive film, a second gate conductive film having a plasma emissioncharacteristic different from that of the first gate conductive film;forming, on a surface of the second gate conductive film, a third gateconductive film having a plasma emission characteristic different fromthat of the second gate conductive film; flattening respective upperportions of the first, second and third gate conductive films; andanisotropically etching the first, second and third gate conductivefilms, wherein the second gate conductive film is formed to becomethinner than the first and third gate conductive films, and an intensityof plasma emission generated from the second gate conductive film ismonitored during the etching to detect a change in the plasma emissionintensity occurring when the second gate conductive film is etched away,to thereby detect an end-point of the etching for the first, second andthird gate conductive films.

Preferably, in the method according the second aspect of the method, thefirst gate conductive film and the third gate conductive film are madeof an identical material.

Preferably, in the method according to the second or third aspect of thepresent invention, the pillar-shaped semiconductor layer has a thirdprotective film formed on a top thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1( a) and 1(b) are, respectively, a top plan view and a sectionalview of an SGT produced by a production method according to a firstembodiment of the present invention.

FIGS. 2( a) and 2(b) are process diagrams showing the production processaccording to the first embodiment, on a step-by-step basis.

FIGS. 3( a) and 3(b) are process diagrams showing the production processaccording to the first embodiment, on a step-by-step basis.

FIGS. 4( a) and 4(b) are process diagrams showing the production processaccording to the first embodiment, on a step-by-step basis.

FIGS. 5( a) and 5(b) are process diagrams showing the production processaccording to the first embodiment, on a step-by-step basis.

FIGS. 6( a) and 6(b) are graphs showing characteristic curves of aplasma emission intensity in the production process according to thefirst embodiment.

FIGS. 7( a) and 7(b) are process diagrams showing a production processaccording to a second embodiment of the present invention, on astep-by-step basis.

FIGS. 8( a) and 8(b) are process diagrams showing the production processaccording to the second embodiment, on a step-by-step basis.

FIGS. 9( a) and 9(b) are process diagrams showing the production processaccording to the second embodiment, on a step-by-step basis.

FIGS. 10( a) and 10(b) are process diagrams showing the productionprocess according to the second embodiment, on a step-by-step basis.

FIGS. 11( a) and 11(b) are process diagrams showing the productionprocess according to the second embodiment, on a step-by-step basis.

FIGS. 12( a) and 12(b) are process diagrams showing the productionprocess according to the second embodiment, on a step-by-step basis.

FIGS. 13( a) and 13(b) are process diagrams showing the productionprocess according to the second embodiment, on a step-by-step basis.

FIGS. 14( a) and 14(b) are process diagrams showing the productionprocess according to the second embodiment, on a step-by-step basis.

FIGS. 15( a) and 15(b) are process diagrams showing a production processaccording to a third embodiment of the present invention, on astep-by-step basis.

FIGS. 16( a) and 16(b) are process diagrams showing the productionprocess according to the third embodiment, on a step-by-step basis.

FIGS. 17( a) and 17(b) are process diagrams showing the productionprocess according to the third embodiment, on a step-by-step basis.

FIGS. 18( a) and 18(b) are process diagrams showing the productionprocess according to the third embodiment, on a step-by-step basis.

FIG. 19 is a graph showing a characteristic curve of a plasma emissionintensity in the production process according to the third embodiment.

FIGS. 20( a) to 20(b) are, respectively, a top plan view and a sectionalview of a conventional SGT.

FIGS. 21( a) to 21(h) are diagrams showing a conventional SGT productionmethod.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An SGT production method capable of detecting an etching end-point bymonitoring a plasma emission intensity during dry etching for apillar-shaped silicon layer and a gate electrode will now be described

First Embodiment

A first embodiment of the present invention provides a method for, in anoperation of forming a pillar-shaped silicon layer by dry etching,accurately controlling an etching amount of the pillar-shaped siliconlayer, using an end-point detection process based on monitoring of aplasma emission intensity.

FIG. 1( a) is a top plan view showing an NMOS SGT produced by the methodaccording to the first embodiment, and FIG. 1( b) is a sectional viewtaken along the line A-A′ in FIG. 1( a). With reference to FIGS. 1( a)and 1(b), the SGT produced by the method according to the firstembodiment will be described below.

A pillar-shaped silicon layer 102 is formed on a silicon substrate 101,and a gate dielectric film 105 and a gate electrode 106 a are formedaround the pillar-shaped silicon layer 102. An N⁺ drain diffusion layer103 is formed underneath the pillar-shaped silicon layer 102, and an N⁺source diffusion layer 104 is formed on a top of the pillar-shapedsilicon layer 102. A contact 107, a contact 108, and a contact 109, areformed on the N⁺ drain diffusion layer 103, the N⁺ source diffusionlayer 104, and a gate line 106 b extending from the gate electrode 106a, respectively.

Under conditions that the N⁺ source diffusion layer 104 is connected toa GND potential, and the N⁺ drain diffusion layer 103 is connected to apower supply potential Vcc, a potential ranging from zero to Vcc isapplied to the gate electrode 106 a to allow the SGT to operate as atransistor. Actually, respective functions of the source diffusion layerand the drain diffusion layer are interchanged in some operatingconditions.

FIGS. 2( a) to 5(b) show one example of the production method whichallows accurate etching for a pillar-shaped silicon layer. In FIGS. 2(a) to 5(b), the figure suffixed with (a) is a top plan view, and thefigure suffixed with (b) is a sectional view taken along the line A-A′in the figure suffixed with (a).

As shown in FIGS. 2( a) and 2(b), a pad oxide film 115 is formed on asilicon substrate 101 to reduce a stress between the silicon substrateand an after-mentioned hard mask. Subsequently, a silicon nitride film110 serving as a first hard mask is formed, and then a silicon-germaniumfilm 111 serving as a second hard mask is formed.

As shown in FIGS. 3( a) and 3(b), a resist is patterned by lithographyusing a mask for a pillar-shaped silicon layer, and then the pad oxidefilm 115, the first hard mask 110 and the second hard mask 111 arepatterned by dry etching.

As shown in FIGS. 4( a) and 4(b), a pillar-shaped silicon layer 102 isformed by dry etching using the first and second hard masks 110, 111 asa mask. FIGS. 4( a) and 4(b) show a structure during the etching. Duringthe etching, the pillar-shaped silicon layer is gradually formed alongwith progress of etching against the silicon substrate, andsimultaneously the second hard mask 111, i.e., a silicon-germanium film,is gradually etched at approximately the same etching rate as that ofthe silicon substrate. When the etching is further progressed, and aremaining small part of the second hard mask starts to be furtheretched, a plasma emission intensity of germanium will decrease. Thus, anetching end-point can be detected. FIG. 6( a) is a graph schematicallyshowing a characteristic curve of the plasma emission intensity ofgermanium. When the etching is started at the time indicated by “Start”in FIG. 6( a), the plasma emission intensity of germanium sharplyincreases. Then, when only a small part of the silicon-germanium film asthe second hard mask is left due to the progress of etching at the timeA1 in FIG. 6( a), the plasma emission intensity of germanium startsdecreasing. The etching end-point can be detected by monitoring thedecrease in the plasma emission intensity of germanium. Even if anetching rate for forming the pillar-shaped silicon layer is differentfrom that of the second hard mask, there is no problem as long as theend-point can be detected based on the second hard mask before thepillar-shaped silicon layer is formed by etching to have a desiredheight dimension.

In case where the second hard mask is made of polysilicon, instead ofgermanium, it is also possible to detect the etching end-point. In thiscase, the etching end-point can be detected by monitoring a plasmaemission intensity of silicon. FIG. 6( b) is a graph schematicallyshowing a characteristic curve of the plasma emission intensity ofsilicon. When etching is started at the time indicated by “Start” inFIG. 6( b), the plasma emission intensity of silicon sharply increases.Then, when only a small part of the polysilicon film as the second hardmask is left due to the progress of etching at the time A2 in FIG. 6(b), an amount of silicon to be etched declines by the decrease in thesecond hard mask, and thereby the plasma emission intensity of siliconalso decreases by just that much. The etching end-point can be detectedby monitoring the decrease in the plasma emission intensity of silicon.

As shown in FIGS. 5( a) and 5(b), after completion of the dry etching,the second hard mask is completely etched away, and the pillar-shapedsilicon layer 102 is formed. Further, an upper portion of thepillar-shaped silicon layer 102 is protected from the etching, by thefirst hard mask 110. In order to obtain a pillar-shaped silicon layerhaving a desired height dimension, the etching may be continued for aspecific time which is calculated in consideration of an etching ratefor an etching operation after the detection of the etching end-point.

In the first embodiment, silicon-germanium and polysilicon are shown asa material of the second hard mask. Alternatively, the second hard maskmay be made of any other suitable material allowing an etching end-pointto be detected in the above manner, such as amorphous silicon. Further,a silicon nitride film is shown as the first hard mask. Alternatively,the first hard mask may be any other suitable film capable of protectingan upper portion of the pillar-shaped silicon layer from the etching.

Second Embodiment

A second embodiment of the present invention provides a method for, inan operation of forming a gate electrode by dry etching, accuratelycontrolling an etching amount of the gate electrode, using an end-pointdetection process based on monitoring of a plasma emission intensity. AnSGT to be produced by the method according to the second embodiment hasthe same structure as that illustrated in FIGS. 1( a) and 1(b).

FIGS. 7( a) to 14(b) show one example of the SGT production method basedon accurate etching for a gate electrode. In FIGS. 7( a) to 14(b), thefigure suffixed with (a) is a top plan view, and the figure suffixedwith (b) is a sectional view taken along the line A-A′ in the figuresuffixed with (a).

FIGS. 7( a) and 7(b) show a configuration before forming a gateconductive film. An N⁺ diffusion layer 103 is formed in a diffusionregion beneath a pillar-shaped silicon layer, by impurity implantationor the like.

As shown in FIGS. 8( a) and 8(b), a gate dielectric film 105 is formed.Then, a first gate conductive film 106 is made, for example, ofpolysilicon, and formed to cover the gate dielectric film 105 and have afilm thickness greater than a desired gate length. Then, a second gateconductive film 112 is made, for example, of silicon-germanium, andformed to cover the first gate conductive film 106. In this manner, thegate dielectric film 105, the first gate conductive film 106 and thesecond gate conductive film 112 are formed in this order to allow thepillar-shaped silicon layer 102 to be buried therein.

As shown in FIGS. 9( a) and 9(b), respective portions of the first andsecond gate conductive films 106, 112 and the gate dielectric film 105above the pillar-shaped silicon layer 102 are polished by CMP, toflatten respective top surfaces of the first and second gate conductivefilms. The flattening of a top of the first and second gate conductivefilms by CMP facilitates control of the gate length. During the CMP, afirst hard mask 110 on the top of the pillar-shaped silicon layer isused as a CMP stopper. A silicon nitride film may be used as the firsthard mask. In this case, a selectivity ratio between the first hard maskand each of the first and second gate conductive films can be set to alarge value to control a CMP amount with high repeatability.

As shown in FIGS. 10( a) and 10(b), the first and second gate conductivefilms 106, 112 are etched back to set the gate length. FIGS. 10( a) and10(b) show a structure during the etching. Preferably, during theetching, the first gate conductive film 106, i.e., a polysilicon film,and the second gate conductive film 112, i.e., a silicon-germanium film,are etched at the same etching rate. When the etching is progressed upto a position close to a boundary between the first and second gateconductive films 106, 112 in a vertical direction, and only a small partof the silicon-germanium film as the second gate conductive film 112 isleft, a plasma emission intensity of germanium starts decreasing, sothat an etching end-point can be detected. In this case, the same plasmaemission characteristic as that in FIG. 6( a) is exhibited. As above, anetching end-point detection process in the second embodiment is intendedto detect the vertical boundary between the first and second gateconductive films 106, 112 in the vertical direction. An upper portion ofthe pillar-shaped silicon layer 102 is protected from the etching, bythe first hard mask 110.

In case where a stepped portion is formed between the diffusion layerunderneath the pillar-shaped silicon layer and an element isolationregion, there can be a plurality of boundaries between the first andsecond gate conductive films 106, 112 in the vertical direction. In thiscase, a setting of an algorithm for the end-point detection may beadjusted to detect an etching end-point based on one of the boundarieswhich is first exposed, or may be adjusted to detect the etchingend-point based on one of the remaining boundaries which is subsequentlyexposed.

In case where each of the first and second gate conductive films is madeof a metal, the first gate conductive film and the second gateconductive film may be made, respectively, of tantalum nitride andtitanium nitride, to detect an etching end-point in the same manner.Further, in place of the second gate conductive film, a dielectric film,such as a silicon oxide film, may be used. As substitute for the abovematerials, any other suitable conductive material may be selected, aslong as each of the first and second conductive films exhibits adifferent plasma emission characteristic to allow an etching end-pointto be detected in the above manner.

As shown in FIGS. 11( a) and 11(b), after completion of the dry etching,the second gate conductive film 112 in a gate electrode region aroundthe pillar-shaped silicon layer is completely etched away, and a gateelectrode is formed by the first gate conductive film 106. Therefore,the first gate conductive film 106 should be initially formed to have athickness greater than the final gate length.

As shown in FIGS. 12( a) and 12(b), the pad oxide film 115 and the firsthard mask is removed by dry etching or wet etching. Then, the first gateconductive film is patterned to form a gate electrode surrounding thepillar-shaped silicon layer, and a gate line on which a contact or thelike is to be formed.

As shown in FIGS. 13( a) and 13(b), a diffusion layer 104 is formed inan upper portion of the pillar-shaped silicon layer, by impurityimplantation or the like.

As shown in FIGS. 14( a) and 14(b), an interlayer film is formed, and acontact (107, 108, 109) is formed. In the above manner, a transistor isformed.

Third Embodiment

A third embodiment of the present invention provides another method for,in an operation of forming a gate electrode by dry etching, accuratelycontrolling an etching amount of the gate electrode, using an end-pointdetection process based on monitoring of a plasma emission intensity. AnSGT to be produced by the method according to the third embodiment hasthe same structure as that illustrated in FIGS. 1( a) and 1(b).

FIGS. 7( a) to 14(b) show one example of the SGT production method basedon accurate etching for a gate electrode. In FIGS. 7( a) to 14(b), thefigure suffixed with (a) is a top plan view, and the figure suffixedwith (b) is a sectional view taken along the line A A′ in the figuresuffixed with (a).

FIGS. 15( a) and 15(b) show a sectional structure after forming a gateconductive film. In the third embodiment, the gate conductive filmcomprises a first gate conductive film, a second gate conductive filmand a third gate conductive film. The first gate conductive film 206 ismade, for example, of polysilicon, and formed to have a film thicknessgreater than a desired gate length. The second gate conductive film 212is made, for example, of silicon-germanium, and formed to cover thefirst gate conductive film 206. The third gate conductive film 213 ismade, for example, of polysilicon, and formed to cover the second gateconductive film 212 and have a film thickness greater than that of thesecond gate conductive film 212. In this manner, the first gateconductive film 206, the second gate conductive film 212 and the thirdgate conductive film 213 are formed in this order to allow apillar-shaped silicon layer 202 to be buried therein.

As shown in FIGS. 16( a) and 16(b), respective portions of the first tothird gate conductive films and a gate dielectric film 205 above thepillar-shaped silicon layer are polished by CMP, to flatten respectivetop surfaces of the first to third gate conductive films. The flatteningof a top of the first to third gate conductive films by CMP facilitatescontrol of the gate length. During the CMP, a first hard mask 210 on atop of the pillar-shaped silicon layer is used as a CMP stopper. Asilicon nitride film may be used as the first hard mask 210. In thiscase, a selectivity ratio between the first hard mask and each of thefirst to third gate conductive films can be set to a large value tocontrol a CMP amount with high repeatability.

As shown in FIGS. 17( a) and 17(b), the first to third gate conductivefilms are etched back to set the gate length. FIGS. 17( a) and 17(b)show a structure during the etching. Preferably, during the etching, thefirst gate conductive film 206, i.e., a polysilicon film, the secondgate conductive film 212, i.e., a silicon-germanium film, and the thirdgate conductive film 213, i.e., a polysilicon film, are etched at thesame etching rate.

When the etching is progressed, and at least a part of a surface of thesecond gate conductive film 212, i.e., the silicon-germanium film, isexposed, a plasma emission intensity of germanium starts increasing, sothat an etching end-point can be detected. FIG. 19 is a graphschematically showing a characteristic curve of the plasma emissionintensity of germanium. Just after the etching is started at the timeindicated by “Start” in FIG. 19, the intensity of plasma emission fromthe second gate conductive film 212, i.e., the silicon-germanium film,is significantly weak. Then, when the surface of the silicon-germaniumfilm starts to be exposed, the plasma emission intensity of germaniumsharply increases. Then, when the silicon-germanium film is furtheretched, and only a small part of the silicon-germanium film is left, theplasma emission intensity of germanium decreases again. The etchingend-point can be detected by monitoring the increase in plasma emissionintensity at the time indicated by A3 in FIG. 19.

In case where a stepped portion is formed between a diffusion layerunderneath the pillar-shaped silicon layer and an element isolationregion, there can be a plurality of boundaries between the first andsecond gate conductive films 206, 212 in a vertical direction. In thiscase, a setting of an algorithm for the end-point detection may beadjusted to detect an etching end-point based on one of the boundarieswhich is first exposed, or may be adjusted to detect the etchingend-point based on one of the remaining boundaries which is subsequentlyexposed.

As shown in FIGS. 18( a) and 18(b), after completion of the dry etching,the second and third gate conductive films in a gate electrode regionaround the pillar-shaped silicon layer are completely etched away, and agate electrode is formed by the first gate conductive film. Therefore,the first gate conductive film 206 should be initially formed to have athickness greater than the final gate length.

In the third embodiment, a silicon-germanium film is used as the secondgate conductive film. In place of the second gate conductive film, adielectric film, such as a silicon oxide film, may be used. Further, incase where each of the first to third gate conductive films is made of ametal, the first gate conductive film, the second gate conductive filmand the third gate conductive film may be made, respectively, oftantalum nitride, titanium nitride and tantalum nitride to detect anetching end-point in the same manner. As substitute for the abovematerials, any other suitable conductive material may be selected, aslong as an etching end-point can be detected based on a plasma emissioncharacteristic in the above manner.

As described above, in the production method of the present invention,during dry etching for forming a pillar-shaped silicon layer and a gateelectrode of an SGT, an etching amount can be controlled using anend-point detection process, so that the SGT can be produced whilestabilizing a height dimension of the pillar-shaped semiconductor layer,and a gate length. This makes it possible to produce an SGT havingstable characteristics.

1. A method of producing a semiconductor device in which a sourcediffusion layer, a drain diffusion layer and a pillar-shapedsemiconductor layer are vertically arranged on an upper side of asubstrate in a layered manner, and a gate is arranged around a sidewallof the pillar-shaped semiconductor layer, wherein the pillar-shapedsemiconductor layer is arranged on a semiconductor substrate, thepillar-shaped semiconductor layer has a third protective film formed ona top thereof, and a dielectric film is arranged on respective surfacesof the semiconductor substrate and the pillar-shaped semiconductorlayer, the method comprising the steps of: forming a first gateconductive film to cover a surface of the dielectric film; forming, on asurface of the first gate conductive film, a second gate conductive filmhaving a plasma emission characteristic different from that of the firstgate conductive film; flattening respective upper portions of the firstand second gate conductive films by CMP, the third protective film beingused as a stopper of CMP; and anisotropically etching the first andsecond gate conductive films, wherein an intensity of plasma emissiongenerated from the second gate conductive film is monitored during theetching to detect a change in the plasma emission intensity occurringwhen the second gate conductive film is etched away, to thereby detectan end-point of the etching for the first and second gate conductivefilms.
 2. A method of producing a semiconductor device in which a sourcediffusion layer, a drain diffusion layer and a pillar-shapedsemiconductor layer are vertically arranged on an upper side of asubstrate in a layered manner, and a gate is arranged around a sidewallof the pillar-shaped semiconductor layer, wherein the pillar-shapedsemiconductor layer is arranged on a semiconductor substrate, thepillar-shaped semiconductor layer has a third protective film formed ona top thereof, and a dielectric film is arranged on respective surfacesof the semiconductor substrate and the pillar-shaped semiconductorlayer, the method comprising the steps of: forming a first gateconductive film to cover a surface of the dielectric film; forming, on asurface of the first gate conductive film, a second gate conductive filmhaving a plasma emission characteristic different from that of the firstgate conductive film; forming, on a surface of the second gateconductive film, a third gate conductive film having a plasma emissioncharacteristic different from that of the second gate conductive film;flattening respective upper portions of the first, second and third gateconductive films by CMP, the third protective film being used as astopper of CMP; and anisotropically etching the first, second and thirdgate conductive films, wherein the second gate conductive film is formedto become thinner than the first and third gate conductive films, and anintensity of plasma emission generated from the second gate conductivefilm is monitored during the etching to detect a change in the plasmaemission intensity occurring when the second gate conductive film isetched away, to thereby detect an end-point of the etching for thefirst, second and third gate conductive films.
 3. The method as definedin claim 2, wherein the first gate conductive film and the third gateconductive film are made of an identical material.